It has been customary to employ a hardware emulator using a programmable device such as FPGA or CPLD for verification of operation of a digital LSI. However, as a circuit scale becomes larger and larger year by year, it is getting difficult to allocate the entire digital LSI to one programmable device. Accordingly, some technology has been proposed to resolve such a problem.
For example, Japanese laid-open patent publication No. 11-134385 discloses a method of allocating a circuit to be tested to a plurality of programmable devices. In this method, when the circuit to be tested is to be divided, allocation is performed such that a net having a timing margin of a path delay which is not more than a predetermined value does not extend between programmable devices, from the viewpoint of the fact that a path delay extending between programmable devices becomes a critical path in many cases.
However, the circuit allocation method disclosed by Patent Document 1 does not take into consideration a signal that needs to transmit a change to circuits divided in a plurality of programmable devices at the same time. Accordingly, some circuits, particularly some synchronous circuits, cannot be verified correctly, This problem becomes significant when a clock signal of a digital LSI is distributed. Conventional problems will be described below with use of specific examples.
FIG. 1 is a block diagram showing an example in which a circuit 101 to be verified is divided into two parts, which are allocated to programmable devices 1 and 2, respectively. The circuit 101 to be verified is formed by three cascaded flip-flop circuits A, B, and C. Here, a highest circuit 102 having the flip-flop circuits (FF) A and C is allocated to the programmable device 1, and a circuit part having the flip-flop circuit B is allocated to the programmable device 2.
A clock signal CLK generated by a clock generator 103 is supplied through internal wiring of the programmable device 1 to clock inputs of the flip-flop circuits A and C and supplied from a clock output terminal of the programmable device 1 through wiring between the programmable devices to the programmable device 2. Data at a data output terminal D1 of the flip-flop circuit A is transferred through internal wiring of the programmable devices and wiring between the programmable devices to a data input terminal of the flip-flop circuit B in the programmable device 2. Further, data at a data output terminal D2 of the flip-flop circuit B is transferred through internal wiring of the programmable devices and wiring between the programmable devices to a data input terminal of the flip-flop circuit C in the programmable device 1.
In such an arrangement in which three cascaded flip-flops are implemented in the programmable devices 1 and 2, outputs of the respective flip-flops are shifted from their inputs by one clock cycle if delays of wiring and devices are ideal. Accordingly, data at a data output terminal of the third flip-flop circuit C should have a delay of three cycles as compared to a data input terminal D0 of the first flip-flop circuit A.
Practically, however, there are delays in all circuit elements and wiring. Specifically, there is a delay DY from the data output terminal D1 of the flip-flop circuit A to the data input terminal of the flip-flop circuit B. There is a delay DX from a CLK input terminal of the programmable device 1 to a clock terminal of the flip-flop circuit B.
A problem arises when an input of a clock signal CLK to the flip-flop circuit B has a large delay as compared to timing of the data input (DX>DY). As described above, when data x0 is latched by the flip-flop circuit A, and the data x0 appears on the output terminal D1. Then, the data x0 appears on the data input terminal of the flip-flop circuit B after a delay of DY. Since a clock signal CLK having a delay of DX is then inputted to the clock input terminal of the flip-flop circuit B, the flip-flop circuit B latches the data input x0 at that time. Under the influence of this behavior, a final data output of the flip-flop circuit C varies one cycle earlier than a normal output.
Such abnormal operation is caused by the fact that the clock input of the flip-flop circuit B is delayed from the data input of the flip-flop circuit B. Since the technology disclosed by Patent Document 1 as described above does not take into consideration a signal to be given at the same time, such as a clock signal, it cannot avoid occurrence of the aforementioned abnormal operation and cannot perform a circuit verification correctly.
It is, therefore, an object of the present invention to provide a circuit verification apparatus, a circuit verification method, and a signal distribution method for the same which can correctly verify a circuit to be tested.